1. Field of the Invention
The invention relates to the field of semiconductor integrated-circuit devices and manufacturing, and in particular to structures for enhancing miniature transistor manufacturability and performance.
2. Related Art
Semiconductor integrated-circuit (IC) manufacturers face growing challenges to accurately and reliably produce ever-smaller transistors in order to improve the cost and performance (speed and/or functionality) of modern electronic devices. The most basic building block used in a digital IC device is the metal-oxide-semiconductor field effect transistor (MOSFET). As MOSFETs are scaled below 100 nm in minimum lateral dimension (i.e., the minimum feature size such as the gate length is less than 100 nm), size-related performance and manufacturing issues become increasingly significant.
For example, the short gate lengths in modern MOSFETs can result in relatively large source-to-drain leakage currents. Such leakage currents can cause ICs incorporating those MOSFETs to exhibit undesirably large static power consumption. Conventional efforts to suppress source-to-drain leakage current typically involve increasing the net dopant concentration in the channel region (e.g., to a net dopant concentration greater than 1018 atoms/cm3), increasing gate capacitance, and decreasing the depths of the source and drain junctions adjacent to the channel. A high net dopant concentration in the channel region serves to confine the drain-induced lateral electric field to the drain region, and thereby minimizes the effect of drain bias on the electric potential in the channel region near to the source. At the same time, by increasing the capacitive coupling between the gate electrode and the channel region (e.g., by decreasing the thickness of the gate dielectric), dominant control over the channel potential (i.e., controlling whether the transistor is on or off) is maintained by the gate electrode rather than the drain, thereby allowing the gate-induced electric field to more effectively suppress source-to-drain leakage current. By keeping the depths of the source and drain junctions adjacent to the channel shallower than the length of the channel region, sub-surface leakage currents can be suppressed.
Unfortunately, decreasing the gate dielectric thickness leads to undesirable leakage between the gate electrode and channel region. Furthermore, carrier mobility in the small channel regions of modern MOSFETS can be significantly degraded by high dopant concentration, which results in lower “on-current” for the transistor. The parasitic series resistance of the source and drain regions increases with decreasing junction depth, which also results in lower on-current for the transistor. Therefore, as steps are taken in modern MOSFET designs to reduce static power consumption (i.e., reduce source-to-drain leakage current), overall transistor performance (i.e., on-current) can suffer.
Another problem associated with smaller MOSFET dimensions relates to the sensitivity of device performance to dimensional variation. For devices formed using 180 nm technology generation (and below) processes, relatively small differences in, for example, gate length can result in significant performance differences. However, the IC manufacturing processes used to create those devices (e.g., optical lithography) are unable to provide the device-to-device dimensional consistency required to render such performance differences negligible. Consequently, circuit designers must design for worst-case scenarios to accommodate the wide range of device performance levels, thereby sacrificing overall IC performance to accommodate manufacturability concerns.
Accordingly, it is desirable to provide structures and methods that allow high-performance, low-static-power, and low-variability sub-100 nm MOSFET production.